In digital transmission systems, in order to prevent having long sequences of ones or zeros, it is normal to vary the binary pattern by means of a scrambler.
Scrambling used to be done serially, and this is why the CCITT Recommendation G.709 describes the functional diagram of a 7-bit series synchronous frame scrambler, as well as the polynomial for generating the pseudorandom code and the values of initialization of the corresponding scrambler.
Nevertheless, as the operating frequency of digital transmission systems grew, serial scrambling techniques were no longer applicable. For example, in high definition television transmission systems, it is necessary to work at 2.48 Gbit/s; with serial scrambling, this would mean working at frequencies of around 2.5 GHz, which is not feasible with silicon-based integrated circuits.
The problem of the working frequency could be resolved by using parallel scrambling techniques.
There are various publications in which such techniques for parallel scrambling are described. Specifically, in the article "Parallel scrambling techniques for digital multiplexers" by DooWhan Choi, published in the AT&T Technical Journal, Volume 65, No. 5, September/October 1986, a description of various methods for implementing this parallel scrambling is given.
A common characteristic of all well-known solutions to date, is that the number of inputs of the modulo-2 adders used in the feedback loops of the pseudorandom code generator is not 2 for every one of the modulo-2 additions.
This fact means that the operation of modulo-2 addition has to be carried out in various steps, and this involves two inconveniences that can become decisive.
On one hand, having to perform the modulo-2 addition in more than one step, leads to an increase in the processing delay (actually a multiplication by the number of steps), and this fixes the maximum working rate; or, in other words, for higher working rates, this solution is not valid. Secondly, to use more steps means using more logic gates with the resulting increase in the surface area of the integrated circuit used and, consequently, in the manufacturing cost.